1. Technical Field
The present invention relates to a semiconductor storage device.
2. Related Art
Semiconductor storage devices of the related art are disclosed, for example, in Japanese Laid-open Patent Publication NO's H 11-7776, H8-7574, and H10-27476. The semiconductor storage device disclosed in Japanese Laid-open Patent Publication NO. H11-7776 is equipped with an SRAM cell constructed from six transistors. Namely, in addition to four transistors constituting a latch circuit, the SRAM cell also has two pass transistors provided between the latch circuit and bit lines on either side.
With semiconductor storage devices configured in this manner, since a plurality of SRAM cells are controlled by a single word line, cells other than a target cell are selected when a certain word line is selected. This means that unnecessary pre-charging and discharging are carried out at the time of read and write operations because the cells other than the target cell discharge bit lines connected to the cells. This causes power consumption of the semiconductor storage device to increase.
With regards to this, semiconductor storage devices with pass transistors provided doubly are disclosed in Japanese Laid-open Patent Publication NO's H8-7574, and H10-27476. Here, two pass transistors are connected in series between a latch circuit and each bit line. With semiconductor storage devices of this configuration, it is possible to select only the target cell by controlling these two transistors using individual word lines and resulting increases in power consumption can therefore be suppressed.